- Work with researchers and architects defining verification plans for each of the different core IP.
- Define and track detailed test plans for the different modules and top levels.
- Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage.
- Debug, root-cause and resolve functional failures in the design, partnering with the Design team.
- Collaborate with cross-functional teams including Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality.
- Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry.
- Provide technical mentorship, plan work assignments, and manage performance reviews for design verification engineers on the team.
- Requires a Master's degree (or foreign degree equivalent) in Computer Science, Engineering, Information Systems, Analytics, Mathematics, Physics, Applied Sciences, or a related field and 5 years of experience in the job offered or in a computer-related occupation.
- Requires 5 years of experience in the following:
- 1. Experience in HDL language (System Verilog, or Verilog), and scripting language (TCL, Python, Perl, or Shell-scripting)
- 2. Design Verification in Verification methodologies (UVM or OVM) creating test plans, constrained random verification, Functional Coverage development
- 3. Experience in C/C++/SystemC for Bit Accurate and Transaction Accurate Modeling etc.
- 4. Skills to Architect UVM-based reusable test benches with components for stimulus, checkers, and reference models and
- 5. Experience in block/IP/SoC/full chip level verification.
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