- Drive the top-level architecture of next generation IPs and SOCs.
- Understand in-house IP needs and steer early architecture by assisting with algorithm development and evaluation.
- Influence micro-architecture details for optimal Performance, Power, Area (PPA) working cross-functionally with IP, Design, Implementation, Software, and Product.
- Lead logic development, develop RTL and drive chip level integration.
- Supervise the RTL-to-GDS flow and assist with synthesis and timing closure to meet frequency, power and area goals.
- Support the test program development, chip validation, and chip life until production maturity.
- In addition to working with FPGA engineers to perform early prototyping, support hand-off and integration of blocks into larger SOC environments.
- Employer will accept a Master’s degree in Computer Science, Electrical Engineering, Electrical and Computer Engineering, or related field and 24 months of work experience in job offered or in a digital design-related occupation. Requires 24 months of experience in the following:
- 1. Silicon transistor and circuit techniques
- 2. Verilog or VHDL
- 3. Logic design and synthesis
- 4. Static Timing Analysis
- 5. C, C++, Java, Ruby or Perl
- 6. Computer Architecture.
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