We are growing our silicon design engineering team to support research silicon development for RL Research (RL-R) teams. We build small scale research silicon to demonstrate and integrate advanced IP into SOC/ASIC solutions to enable in-system testing and prototyping. The goal is to de-risk new IP and fabrication techniques, to prove advanced architectures and to harden controls/algorithms for next generation AR/VR silicon solutions in support of our industry leading virtual and augmented reality systems. As a Design Verification Engineer (DVEs), you will be a key contributor in planning, reviewing and executing our front-end verification efforts at the IP and sub-system levels. You will collaborate in improving DV methodologies and establishing best practices. Your expertise is needed in all phases of the chip development from DV planning to Gate Level Simulations and final sign off. Collaboration with other DVE is paramount for understanding the DV strategy and plan and executing on the same page and mindset. Our team is developing and implementing the next generation custom and semi-custom digital SOC’s/ASIC’s to drive our industry leading virtual and augmented reality systems.